View NT68P81-D01012_1880752.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nt68p81 usb keyboard micro - controller 1 v 2.0 features n built - in 6502c 8 - bit cpu n 3 mhz cpu operation frequency when oscillator is running at 6 mhz n 6k bytes of otp (one time programming) rom n 256 bytes of sram n one 8 - bit programmable base timer with pre - divider circuit n 29 programmable bi - directional i/ o pins including two external interrupts n 3 led direct sink pins with internal serial resistors n on - chip oscillator (crystal or ceramic resonator) n watch - dog timer reset n built - in power - on reset n usb interface n 3 supported endpoints n remote wakeup provid ed n cmos t echnology for low power consumption n 40 - pin dip package , 42 - pad dice form and cob general description the nt68p81 is a single chip micro - controller for usb keyboard applications. it incorporates a 6502c 8 - bit cpu core, 6k bytes of otp rom, and 256 bytes of ram used as working ram and stack area. it also includes 29 programmable bi - directional i/o pins with built - in resistors, and one 8 - bit pre - loadable base timer. additionally, it includes a built - in power - on reset, a built - in low voltage reset, an oscil lator that requires crystal or ceramic resonator applied, and a watch - dog timer that prevents system standstill. pin configuration pad configuration gnd vcp vdp vdm [oe] p30 [pgm] p31 int0/p32 int1/p33 p34 [a9] p11 [a0] p00 [a2] p02 [a3] p03 p17 [a4] p04 p20 [db0] p21 [db1] p22 [db2] p23 [db3] p25 [db5] p26 [db6] led0 [mode0] led1 [mode1] v dd led2 [mode2] osco osci p12 [a10] p27 [db7] nt68p81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 [vpp] reset [a1] p01 [a5] p05 [a6] p06 [a7] p07 [a8] p10 17 18 19 20 p24 [db4] p16 p15 [ce] p14 [a12] p13 [a11] 24 23 22 21 28 34 nt68p81 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 40 39 38 37 36 35 34 33 32 31 30 29 28 24 23 22 21 20 19 18 17 g n d v c p v d p v d m o s c o v c c l e d 2 p31 p32 p33 p34 reset p00 p01 p02 p03 p04 p 0 5 p20 p21 p22 p23 p24 p25 p26 p27 led0 led1 p 1 5 p 1 4 p 1 3 p 1 2 p 1 1 p 1 0 p 0 7 p 0 6 42 o s c i g n d 1 v c c p30 25 28 27 26 p16 p17
nt68p81 2 block diagra m power down/up 6k bytes otp rom 6502 cpu interrupt controller base timer watch dog timer 256 bytes sram sie fifos serial bus manager vcp vdp vdm led0 led1 led2 p00~p07 p10~p17 p20~p27 p30~p34 osci osco v dd gnd reset timing generator power-on reset transceiver i/o ports
nt68p81 3 pin and pad descriptions pin no. pad no. designation i/o shared with otp[i/o] description 1 1,2 gnd p ground 2 3 vcp o usb 3.3v driver 3 4 vdp i/o usb data plus 4 5 vdm i/o usb data minus bi - directiona l i/o pin 5 6 p30 i/o oe [i] program output enable i/o bi - directional i/o pin 6 7 p31 pgm [i] program control 7 8 p32/int0 i/o bi - directional i/o shared with int0 8 9 p33/int1 i/o bi - directional i/o shared with int1 9 10 p34 i/o bi - directional i/o pin reset i internally pulled down resistor 10 11 vpp [p] program supply voltage p00 ~ p07 i/o bi - directional i/o pin 11 ~ 18 12 ~ 19 a0 ~ a7 [i] program address buffer p10 ~ p14 i/o bi - directional i/o pin 19 ~ 23 20 ~ 24 a8 ~ a12 program address buffer p15 i/o bi - directional i/o pin 24 25 ce [i] program chip enable p16 i/o bi - directional i/o pin 25 26 vpih[i] otp program input voltage high 2 6 27 p17 i/o bi - directi onal i/o pin p20 ~ p27 i/o bi - directional i/o pin 27 ~ 34 28 ~ 35 db0 ~ db7 [i/o] program data buffer led0 o led direct sink 35 36 mode0 [i] mode selection led1 o led direct sink 36 37 mode1 [i] mode selection led2 o led direct sink 37 38 mode2 [i] mode selection 38 39,40 v dd p power supply (+5v) osco o crystal oscillator output 39 41 clk[i] program clock
nt68p81 4 osci i crystal oscillator input 40 42 vpil[i] otp program input voltage low * [ ]: otp mode
nt68p81 5 functional de scription 1. 6502c cpu the 6502c is an 8 - bit cpu that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory range, and an interrupt input. other feature s are also included. the cpu clock cycle is 3mhz (6mhz system clock divided by 2). please refer to 6502 data sheet for more detailed information. accumulator a index register y 0 7 7 index register x 7 0 0 stack pointer sp 0 n status register p 0 7 carry zero irq disable decimal mode brk command overflow negative 7 program counter pch 8 15 7 0 pcl 1 = true 1 = result zero 1 = disable 1 = true 1 = neg 1 = true 1 = brk v b d i z c figure 1. 6502 cpu registers and status flags
nt68p81 6 2.instruction set list instruction code meaning operation adc add with carry a + m + c ? a ?a c and logical and a ?e m ? a asl shift left one bit c ?? m7 ?e?e?e m0 ?? 0 bcc branch if carry clear branch on c ? 0 bcs branch if carry set branch on c ? 1 beq branch if equal to zero branch on z ? 1 bit bit test a ?e m ?a m7 ? n ?a m6 ? v bmi branch if minus branch on n ? 1 bne branch if not equal to zero branch on z ? 0 bpl branch if plus branch on n ? 0 brk break forced interrupt pc + 2 ?? pc ?? bvc branch if overflow clear branch on v ? 0 bvs branch if overflow set branch on v ? 1 clc clear carry 0 ? c cld clear decimal mo de 0 ? d cli clear interrupt disable bit 0 ? i clv clear overflow 0 ? v cmp compare accumulator to memory a ?e m cpx compare with index register x x ?e m cpy compare with index register y y ?e m dec decrement memory by one m ?e 1 ? m dex decrement index x by one x ?e 1 ? x dey decrement index y by one y ?e 1 ? y eor logical exclusive - or a ? m ? a inc increment memory by one m + 1 ? m inx increment index x by one x + 1 ? x iny increment index y by one y + 1 ? y jmp jump to new location (pc + 1) ? pcl ?a (p c + 2) ? pch jsr jump to subroutine pc + 2 ?? ?a (pc + 1) ? pcl ?a (pc + 2) ? pch
nt68p81 7 instruction set list (contiuned) instruction code meaning operation lda load accumulator with memory m ? a ldx load index register x with memory m ? x ldy load index register y with memory m ? y lsr shift right one bit 0 ? m7 ?e?e?e m0 ? c nop no operation no operation (2 cycles) ora logical or a + m ? a pha push accumulator on stack a ?? php push status register on stack p ?? pla pull accumulator from stack a ?? plp pull status register from stack p ?? rol rotate left through carry c ?? m7 ?e?e?e m0 ?? c ror rotate right through carry c ? m7 ?e?e?e m0 ? c rti return from interrupt p ?? ?a pc ?? rts return from subroutine pc ?? ?a pc+1 ? pc sbc subtract with borrow a ?e m ?e c ? a ?a c sec set carry 1 ? c sed set decimal mode 1 ? d sei set interrupt disable status 1 ? i sta store accumulator in memory a ? m stx store index register x in memory x ? m sty store index register y in memory y ? m tax transfer accumulator to index x a ? x tay tra nsfer accumulator to index y a ? y tsx transfer stack pointer to index x s ? x txa transfer index x to accumulator x ? a txs transfer index x to stack pointer x ? s tya transfer index y to accumulator y ? a *for more detailed specifications, pleas e refer to 6502 programming data book.
nt68p81 8 3 . otp rom: 6k x 8 bits the built - in otp rom program code, executed by the 6502 cpu, has a capacity of 6k x 8 - bit and is addressed from e800h to ffffh. it can be programmed by the universal eprom writer through a co nversion adapter and programming configuration such as intel - 27c64. in the operating mode, the otp rom is integrated with the system and it cannot be directly accessed. when the user wants to work with the otp rom alone, the user must first enter the p rogramming mode by setting: pin < reset = vpp>. at this time, through multiplex pins, we can use familiar procedures to program and verify the otp rom block with the universal programmer. otp rom mega cell d.c. electrical characteristics (read mode) (v dd = 5v, t a = 25 j , unless otherwise specified) symbol parameter min. typ. max. unit test conditions note v ih input voltage v dd - 0.3 v dd + 0.3 v 1 v il - 0.3 0.3 v 1 i il input current +/ - 10 a i oh output voltage - 400 a v dd = 5v, v oh = 4.5v i ol 1 ma v dd = 5v, v ol = 0.5v i dd operating current 1 ma f = 3m h z 2 i stb1 standby current 100 a 3 note: 1. all inputs and outputs are cmos compatible 2. f = 3mhz, l out = 0ma, ce = v ih . v dd = 5v 3. ce = v ih , oe = v il , v dd = 5v otp rom meg a cell a.c. electrical characteristics (read mode) (v dd = 5v, t a = 25 j , unless otherwise specified) symbol parameter min. max. unit conditions t cyc cycle time 250 ns t 12 non - overlap time to ph1 & ph2 5 65 ns t acc address access time 145 ns t ce otpce to output valid 145 ns 4.5v < v dd < 5.5v t st output data setup t ime 20 ns t oh output data hold time 0 ns otp rom mega cell a.c. test conditions output load 1 cmos gate and cl = 10pf input pulse rise and fall times 10ns max. input pulse levels 0v to 5v timing measurement reference level inputs 0v and 5v outpu ts 0.3v and 4.7v
nt68p81 9 otp rom mega cell timing waveforms (read mode) tcyc t12 tacc & tce tst toh ph1 ph2 a0 - a14 otpce db0 - db7 otp rom mega cell d.c. electrical characteristics (programming mode) (v dd = 5v, t a = 25 j , unless otherwise specified) symbol parameter min. typ. max. unit test conditions note v dd supply voltage 6 6.5 v 4 v pp 10.5 12.75 v v ih input voltage 2 v dd + 0.3 v v il - 0.3 0.6 v i il output current +/ - 10 g a i oh output current - 400 g a v dd = 5v, v oh = 4.5v i ol 1 ma v dd = 5v, v ol = 0.5v i dd operating current 30 ma i pp 20 ma v pp = 12.75v clk input clock 53.203424 mhz vpih input voltage 2 v dd + 0.3 v vpil - 0.3 0.6 v
nt68p81 10 note: 4. for reliability concerns, we suggest v dd = 6v & vpp = 12.75v for testing otp rom ac characteristics in programming mode, and the same condition is suggested for universal programmer supply voltage. otp rom mega cell a.c. electrical characteristics (programming mode) (t a = 25 j , unless otherwise specified) symbol parameter min. typ. max. unit test conditions note t ms mode decode setup time 2 s t mh mode decode hold time 2 s t as address setup time 2 s t ah address hold time 2 s t ces ce setup time 2 s t ceh ce h old time 2 s t ds date setup time 2 s t dh data hold time 2 s t vs v pp setup time 2 s t pw program pulse width 100 s t dv oe to output valid 150 ns t df oe to output high - z 90 ns ce = v il otp rom mega cell a.c. test conditions output load 1 ttl gate and c l = 100pf input pulse rise and fall times 10ns max. input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2.2v outputs 0.8v and 2.4v
nt68p81 11 otp rom m ega cell timing waveform (program) a0 - a14 db0 - db7 ce oe pgm v pp mode dec. test = vpp, mode [0..2] = 000; d in dout tms tmh tds tpw tdh tdv tdf tvs tas tces tceh tah note: 5 . v dd must be applied simultaneously or before vpp and cut off simultaneously or after v pp . 6 . removing the device from the socket or setting the device in socket with v pp = 12.75v may cause permanent damage.
nt68p81 12 o t p rom mega cell mode selection reset = 12.75v, vpil = v il , vpih = v ih mode [0..2] mode ce oe vpp db0 - db7 not vpp ?e normal operating ?e ?e ?e ?e vpp 000 output disable ?e v ih ?e high - z vpp 0 00 program v ih v ih vpp data in vpp 000 program verify v ih v il ?e data out vpp 000 program inhibit (standby) v il ?e vpp high - z vpp 001 security (program) v ih ?e vpp data in vpp 010 word - line stress ?e ?e vpp ?e vpp 011 bit - line stress ?e ?e vpp ?0? vpp 100 ot p row (after pkg) v ih v ih vpp data in vpp 101 otp column (after pkg) v ih v ih vpp data in *the security byte is at $0000 address. read mode the nt68p81's otp rom mega cell has 2 control pins. the ce (chip enable) controls the operation power and is use d for device selection. the oe (output enable) controls the output buffers. output disable mode if oe = v ih , the outputs will be in a high impedance state. so two or more roms can be connected together on a commo n bus. standby mode by applying a low level to the chip is in standby mode, it will reduce the operating current to 100a. program mode initially, all bits are in "1" state which is an erased state. thus the program operation is to introduce "0" data int o the desired bit locations by electronic programming. when the v pp input is at 12.75v and ce is at v ih , the chip is in the programming mode. program verlfy mode the verify mode will check to see that the desired data is correctly programmed on the progr ammed bit. the verify is accomplished with ce at v ih , vpp input is at 12.75v, and oe = v il . program inhibit using this mode, programming of two or more otp roms in parallel with different data is accomplished. all inputs except for ce and oe may be commonly connected. the ttl high level program pulse is only applied to the ce of the desired device and ttl high level signal is applied to the other devices.
nt68p81 13 4. sram: 256 x 8 bits the built - in sram is used for gene ral purpose data memory and for stack area. sram is addressed from 0080h to 017fh. because the 6502c default stack pointer is 01ffh, the stack area will map $01ff - $0180 to $00ff - $0080, thus the programmer can set the ?s? register to 7fh when starting progr am, allowing stack point to be 017fh. as; ldx #$7f txs system registers unused ram ram unused rom $fffa $fffb $fffc $fffd $fffe $ffff nmi vector reset vector irq vector stack pointer $0000 $001f $0080 $00ff $0100 $017f $e800 nmi-l nmi-h rst-l rst-h irq-l irq-h
nt68p81 14 5. system reserved registers address register reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w $0000 irqfunc 00h ?e ?e ?e ?e kbd int1 int0 tmr r $0001 irqclrf 00h ?e ?e ?e ?e ckbd cint1 cint0 ctmr w $0002 ie_ func 00h ?e ?e ?e ?e ekbd eint1 eint0 etmr r/w $0003 irqusb 00h susp stup ?e ?e in2 in1 ot0 in0 r $0004 irqclru 00h csusp cstup ?e ?e cin2 cin1 cot0 cin0 w $0005 ie_ usb 00h esusp estup ?e ?e ein2 ein1 eot0 ein0 r/w $0006 bt 00h bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w $0007 tcon 01h ?e ?e ?e ?e ?e ?e ?e enbt w $0008 tmod 00h ?e ?e ?e ?e ?e tm2 tm1 tm0 r/w $0009 port0 ffh p07 p06 p05 p04 p03 p02 p01 p00 r/w $000a port1 ffh p17 p16 p15 p14 p13 p12 p11 p10 r/w $000b port2 ffh p27 p26 p25 p24 p23 p22 p21 p20 r/w $000c port3 1fh ?e ?e ?e p34 p33 p32 p31 p30 r/w $000d led 07h ?e ?e ?e ?e ?e led2 led1 led0 w $000e clrwdt 00h 0 1 0 1 0 1 0 1 w $000f mode_ fg 02h ?e ?e ?e ?e ?e ?e pof susf r /w ?e : no effect 6. power - on reset built - in power - on reset circuit can generate a minimum of 5ms pulse to reset the entire chip. the user also can use an external reset pin to reset the entire chip. 7. timing generator this block g enerates the system timing and control signals supplied to the cpu and on - chip peripherals. the crystal oscillator generates a 6mhz system clock. it only generates 3mhz clock for cpu.
nt68p81 15 8. base timer (bt) the base timer is an 8 - bit counter with a programm able clock source selection. the bt can be enabled/disabled by the cpu. after reset, the bt is disabled and cleared. the bt can be preset by writing a preset value to bt7 ~ bt0 of the bt register at any time. when the bt is enabled, the bt starts counting from the preset value. when the value reaches ffh, it generates a timer interrupt if the timer interrupt is enabled. when it reaches the maximum value of ffh, the bt will wrap around and begin counting at 00h. the bt can be enabled by writing a "0" to " enbt " bit in the tcon (timer control) register. the enbt signal is level trigger. the input clock source of bt is controlled by the tmod register. the following table shows 8 ranges of the bt. tm2 tm1 tm0 pre - scalar rati o min. count max. count 0 0 0 system clock/2 3 1.33 s 341.33 s 0 0 1 system clock/2 4 2.66 s 682.66 s 0 1 0 system clock/2 5 5.32 s 1.36 ms 0 1 1 system clock/2 6 10.64 s 2.72 ms 1 0 0 system clock/2 7 21.28 s 5.44 ms 1 0 1 system clock/2 8 42.56 s 10.89 ms 1 1 0 system clock/2 9 85.12 s 21.79 ms 1 1 1 system clock/2 10 170.24 s 43.58 ms for counting accuracy, please set the tmod register first, then preset the bt register , and enable the base timer finally . (tm2, tm1, tm0) = (1, 1, 1) is reserve d for usb driver use.
nt68p81 16 9. interrupt controller there are 10 interrupt sources: timer, int0, int1, kbd, susp, in0, in1, in2, ot0 and stup. 9.1. timer interrupt when the base timer overflows, it will set the tmr flag, if the interrupt is enabled by writing "1" to the bit 0 in ie_func ($0002h), then it will interrupt 6502 cpu. the tmr flag can be read by the software. once set by an interrupt source, it can read from bit0 in irqfunc ($0000h ) and remains high unless cleared by writing "1" to the bit 0 in irqcl rf ($0001h). all of register's data is cleared to "0" at initialization by the system reset. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, thus the tmr flag must be cleared by the software. 9.2. int0 interrupt as soon as int0 pin detects a falling edge trigger, nt68p81 sets the int0 flag ($0000h, bit1). after that , the 6502 cpu is interrupted if this interrupt has been already been enabled by writing ?1? to eint0 ($0002h, bit1). if the eint0 flag is c leared, the 6502 cpu can?t be int0 interrupted even if the int0 flag is set. int0 flag can be only be set by hardware and can not be set or cleared directly by the sof t ware except for writing ?1? to cint0 ($0001h, bit1) flag to clear int0 flag. when an int errupt occurs, the cpu will jump to $fffeh & $ffffh to execute the interrupt service routine so the int0 flag must be cleared by software. 9.3. int1 interrupt as soon as the int1 pin detects a falling edge trigger, nt68p81 sets the int1 flag ($0000h, bit2 ). then the 6502 cpu is interrupted if the interrupt has already been enabled by writing ?1? to eint1 ($0002h, bit2). if eint0 flag is cleared, the 6502 cpu can?t be int1 interrupted even if int1 flag is set. int1 flag can only be set by the hardware and can not be set or cleared directly by the software except for writing ?1? to cint1 ($0001h, bit2) flag to clear int1 flag. when an interrupt occurs, cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the int1 flag must be cleared by the software. 9.4. kbd interrupt this interrupt will set the kbd flag ($0000h, bit3) every 4ms(hid 1.00 version) to indicate that keyboard scan data is ready to send for endpoint1. then the 6502 cpu is interrupted if this interrupt has been enabled already b y writing ?1? to ekbd ($0002h, bit3). if the ekbd flag is cleared, the 6502 cpu can?t be kbd interrupted even if the kbd flag is set. the kbd flag can only be set by the hardware and can not be set or cleared directly by the software except for writing ?1 ? to ckbd ($0001h, bit 3) flag to clear kbd flag. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the kbd flag must be cleared by the software. 9.5. in0 token interrupt when an in token for endpoint 0 is done, it will set the in0 flag. if this interrupt is enabled by writing "1" to ein0 ($0005h, bit0), it will interrupt 6502 cpu. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the in0 flag must be clea red by the software. 9.6. ot0 (out 0) token interrupt when an out token for endpoint 0 is done, it will set the ot0 flag. if this interrupt is enabled by writing "1" to eot0 ($0005h, bit1), it will interrupt 6502 cpu. when an interrupt occurs, the cpu jump s to $fffeh & $ffffh to execute the interrupt service routine, the ot0 flag must be cleared by the software.
nt68p81 17 9.7. in1 token interrupt when an in token for endpoint 1 is done, it will set the in1 flag. if this interrupt is enabled by writing "1" to ein1 ($ 0005h, bit2), it will interrupt the 6502 cpu. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the in1 flag must be cleared by the software. 9.8. in2 token interrupt when an in token for endpoint 2 is do ne, it will set the in2 flag. if this interrupt is enabled by writing "1" to ein2 ($0005h, bit3), it will interrupt 6502 cpu. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the in2 flag must be cleared by the software. 9.9. stup (setup) token interrupt when a setup token for endpoint 0 is done, it will set the stup flag. if this interrupt is enabled by writing "1" to estup ($0005h, bit6), it will interrupt 6502 cpu. when an interrupt occurs, the cpu j umps to $fffeh & $ffffh to execute the interrupt service routine, the stup flag must be cleared by the software. 9.10. susp interrupt when usb sie detects a suspend signal, it sets the susp flag. then the 6502 cpu is interrupted if the interrupt has alre ady been enabled by writing ?1? to esusp ($0005h, bit7). if esusp flag is cleared, 6502 cpu can?t be susp interrupted even if susp flag is set. susp flag can be set by h/w only and can?t be set/cleared directly by the software except for writing ?1? to csu sp ($0004h, bit 7) flag to clear susp flag. when an interrupt occurs, the cpu jumps to $fffeh & $ffffh to execute the interrupt service routine, the susp flag must be cleared by the software. 10. i/o ports the nt68p81 has 32 pins dedicated to input and ou tput. these pins are grouped into 5 ports, as follows: port0 (p00~p07) port0 is an 8 - bit bi - directional cmos i/o port that is internally pulled high by pmos. each pin of port0 can be bit programmed as an input or output port under software control. when p rogrammed as output, data is latched to the port data register and output to the pin. port0 pins with ?1? written to them are pulled high by the internal pmos pull - ups, and can be used as inputs in that state, then these input signals can be read. the por t will output high after the reset. port1 (p10~p17) : functions the same as port0. port2 (p20~p27) : functions the same as port0. port3 (p30~p34) : functions the same as port0. except for p33/p32 is shared with int1/int0 pin. it is also a schmitt trigger inp ut with an interrupt source of falling edge sensitive. led: there are three led direct sink pins which require no external serial resistors. the address is mapped to $000dh.
nt68p81 18 11. watch - dog timer (wdt) the nt68p81 has a watch - dog timer reset function th at protects programs against system standstill. the clock of the wdt is derived from the crystal oscillator. the wdt interval is about 0.15 seconds when the operation frequency is 6mhz. the timer must be cleared every 0.15 second during normal operation; o therwise, it will overflow and cause a system reset (this cannot be disabled by the software) . before watch - dog reset occurs, the software will clear the watch - dog register by writing #55h to clrwdt ($000eh) register. for example: lda #$55h sta $000e 12. power control the power - off flag (pof) in the mode_fg register indicates whether a reset is a warm start or a cold start reset. pof is set by hardware when an external power v cc arises to its normal operating level, and must be cleared by the software in the cold reset initialization procedure. a warm start reset (pof = 0) occurs at a watch - dog reset or resume reset. address register reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w $000fh mode_ fg 02h - - - - - - pof susf r/w 13. universal serial bus interface please refer to the universal serial bus specification version 1.0 chapter 7, 8, and 9. 14. suspend and resume suspend: when sie receives the suspend signal, nt68p81 generates a susp interrupt request. in the susp interrup t service routine, the software will carry out the following steps: 1) clear susp irq flag, 2) store all the port status, 3) force return lines (port2) pull - high, 4) force scan lines (port0, port1 and p30, p31 or p32) pull - low, 5) t urn off led output, 6) clear watch - dog re gister after the above action has been completed, the software will then set suslo ($1eh) to #55h and sushi ($1fh) to #aah in order to enter the suspend mode. the oscillator will stop for in order to save power. resume: when the sie detects a resume si gnal, the nt68p81 trigger oscillator to oscillate and resets whole chip. after a reset, software checks the status of pof bit in mode_fg register to see whether a cold start reset or a warm start reset occurred. if cold reset, it executes all initial proce dure. if warm reset, software checks the status of susf bit in mode_ fg register to see whether a watch - dog reset or resume reset. under resume reset condition, programmer should restores all port status. after a warm start, user software should clear the susf bit. when any key stroked in suspend mode, it remotely resume nt68p81 functions. the action is same as host resume.
nt68p81 19 15. reset source summary these are 5 reset sources in nt68p81 as shown below. no. type function description 1 cold external pin ( reset ) applied externally 2 cold power - on reset reset after power - on 3 cold usb reset signaling 10 ms reset period 4 warm - 1 resume reset usb reset period 5 warm - 2 watch - dog reset reset every 0.15s (osc = 6mhz) nt68p81 can also be reset externally through the reset pin. a reset is initialed when the signal at the reset pin is held low for at least 10 system clocks. when reset signal goes high, the nt68p81 begins to work. the followin g shows the definition of reset input low pulse width. 20%v dd 20%v dd v dd trstb v dd 16. ps/2 mouse application a ps/2 mouse interface is implemented in p3 2 (clk) , p3 3 (data) and p34 (power control). the timing diagrams are described as follows. clk data t1 t3 t4 1st clk 2nd clk start bit t1a t2 11th clk 10th clk t5 parity bit stop bit bit 0 auxiliary device sending data timings timing description min/max t1 time from data transaction to falling edge of clk 1 5/25 u s t1a time from data transaction to falling edge of clk 2-11 5/25 u s t2 time from rising edge of clk to data transaction 5/t4-5 u s t3 duration of clk inactive (low) 30/50 u s t4 duration of clk active (high) 30-50 u s t5 time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission >0/50 u s
nt68p81 20 clk data t6 t7 1st clk 2nd clk start bit t8 11th clk 10th clk t9 parity bit stop bit bit 0 auxiliary device receiving data timings timing description min/max t6 duration of clk interface (low) 30/50 u s t7 duration of clk active (high) 30/50 u s t8 time from inactive to active clk transition, used to time when the auxiliary device samples data 5/25 u s t9 time from falling edge of line control bit to falling edge of clock 11 clk 5 u s/ t10 time from rising edge of clock 11 to rising edge of line control bit 5/25 u s t10 line control bit 9th clk i/o inhibit
nt68p81 21 absolute maximum rating* dc supply voltage . . . . . . . . . . . . . . . . . . - 0.3v to +7.0v input/output voltage . . . . . . . .gnd - 0.2v to v dd + 0.2v operating ambient temperatu re . . . . . . . . .0 c to 70 c storage temperature . . . . . . . . . . . . . . - 55 c to +125 c operating voltage (v dd ) . . . . . . . . . . . . .+4.4v to +5.25v *comments stresses above those listed under "absolute maximum rating" may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditi ons for extended periods may affect device reliability. dc electrical characteristics (v dd = 5v, gnd = 0v, t a = 25 c, f osc = 6mhz, unless otherwise noted) symbol parameters min. typ. max. unit conditions v dd operating voltage 4.4 5 5.25 v i op operati ng current 20 m a no load i sp suspend current 500 a v ih input high voltage 2 v v il input low voltage 0.8 v v oh output high voltage 2.4 v i oh = - 100a v ol1 output low voltage (p0/p1/p2) 0.4 v i ol1 = 4ma v ol2 output low voltage (p3) 0. 4 v i ol2 = 5ma i le d led sink current 6 10 14 ma v ol = 3.2v v stih schmitt trigger input high voltage 1.7 2 v v stih schmitt trigger input low voltage 0.8 1.1 v ac electrical characteristics (v dd = 5v, gnd = 0v, t a = 25 c, f osc = 6mhz, unless otherw ise noted) symbol parameters min. typ. max. unit conditions f osc oscillator frequency 5.97 6 6.03 mhz osc within +/ - 0.5% t rstb reset input low pulse width 1.67 m s 10 system clocks t por power - on reset time 5 30 ms usb dc/ac specifications please refer to the universal serial bus specification version 1.0 chapter 7.
nt68p81 22 application circuit 1 (simple keyboard with ps/2 mouse) nt68p81 vcc gnd led0 led1 led2 osci osco vcp num lock caps lock scroll lock to usb cable v cc vdm vdp 4.7 m f 6mhz crystal 10 m f 1.5k o *1 *1 : reset can be direct connect to vcc if the external reset is not used for module test. p20 p21 p22 p23 p24 p25 p26 p27 0.1 m f p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 p00 p01 p02 p03 p04 p05 kor_l d+ d- p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 4.7k o p20 p21 p22 p23 p24 p25 p26 p27 reset p33 r f3 t d f f4 g c v b f2 % 5 $ 4 # 3 e k133 u i y } ] j k h f6 m n < , ^ 6 + = * 8 & 7 k56 o f7 l > . app f8 ( 9 9 pgup + (num) 5 (num) 3 pgdn enter (num) 0 ins . del / (num) * (num) - (num) insert page up page down home end k107 2 8 6 kor_r 7 home 1 end space delete num lock l-shift r-shift 4 p back space : ; { [ | \ (k29) " ' f11 | \ (k42) enter ? / f12 _ - f9 ) 0 f10 k14 l-alt r-alt print screen scroll lock 000 pause l-win r-ctrl l-ctrl f5 00 q w caps lock a s r-win esc k45 z x f1 ~ ` @ 2 ! 1 k131 k132 kor_l kor_r tab p34 p32 ps/2 mouse clk ps/2 mouse data ps/2 mouse power control notice: ?return key? must be forced to port2 for remote wake up function. if not, remote wake up function will not work.
nt68p81 23 application circuit 2 (windows 2000 compatible keyboard) nt68p81 . vcc gnd led0 led1 led2 osci osco vcp num lock caps lock scroll lock to usb cable v cc vdm vdp 4.7 m f 6mhz crystal 10 m f 1.5k o *1 *1 : resetb can be direct connect to vcc if the external reset is not used for module test. p20 p21 p22 p23 p24 p25 p26 p27 0.1 m f p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 p00 p01 p02 p03 p04 p05 power down sleep wake up power down sleep wake up d+ d- euro key bass+ bass- treble+ scan next bass boost scan previous stop play/ pause mute volume+ volume- email www home www search www backward www forward www stop www refresh www favorite treble- media select calculator p32 my computer p32 4.7k o reset p20 p21 p22 p23 p24 p25 p26 p27 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 r u i f3 t y } ] d f j k f4 g h f6 c v m b n f2 < , % 5 ^ 6 + = * 8 & 7 $ 4 # 3 e k133 k56 o 7 home 9 pgup + (num) f7 5 (num) l 1 end 3 pgdn enter (num) space 0 ins . del / (num) * (num) - (num) delete insert page up page down > . num lock app home f8 end ( 9 k107 p back space l-shift : ; { [ | \ (k29) r-shift " ' l-alt f11 | \ (k42) enter ? / r-alt f12 _ - f9 ) 0 print screen f10 scroll lock k14 000 pause q w caps lock l-win a s r-win esc k45 z x f1 r-ctrl l-ctrl ~ ` @ 2 ! 1 f5 00 k131 k132 kor_l kor_r 2 8 6 4 tab notice: ?return key? must be forced to port2 for remote wake up function. if not, remote wake up function will not work.
nt68p81 24 application circuit 3 (mini keyboard) nt68p81 . vcc gnd led0 led1 led2 osci osco vcp num lock caps lock scroll lock to usb cable v cc vdm vdp 4.7 m f 6mhz crystal 10 m f 1.5k o *1 *1 : resetb can be direct connect to vcc if the external reset is not used for module test. p20 p21 p22 p23 p24 p25 p26 p27 0.1 m f p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 p00 p01 p02 p03 p04 p05 power down sleep wake up power down sleep wake up d+ d- euro key bass+ bass- treble+ scan next bass boost scan previous stop play/ pause mute volume+ volume- email www home www search www backward www forward www stop www refresh www favorite treble- media select calculator p32 my computer p32 4.7k o reset p20 p21 p22 p23 p24 p25 p26 p27 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p30 p31 r u i f3 t y } ] d f j k f4 g h f6 c v m b n f2 < , % 5 ^ 6 + = * 8 & 7 $ 4 # 3 e k133 k56 o 7 home 9 pgup + (num) f7 5 (num) l 1 end 3 pgdn enter (num) space 0 ins . del / (num) * (num) - (num) delete insert page up page down > . num lock app home f8 end ( 9 k107 p back space l-shift : ; { [ | \ (k29) r-shift " ' l-alt f11 | \ (k42) enter ? / r-alt f12 _ - f9 ) 0 print screen f10 scroll lock k14 000 pause q w caps lock l-win a s r-win esc k45 z x f1 r-ctrl l-ctrl ~ ` @ 2 ! 1 f5 00 k131 k132 kor_l kor_r 2 8 6 4 tab *fn_k3 *fn_k4 *fn_k2 *fn_k6 *fn_k7 *fn_k8 *4 *5(num) *6 *1 end *2 *3 pgdn *0 ins *. del *fn_k21 *fn_k22 *fn_k16 *fn_k19 *fn_k17 *fn_k20 *fn_k15 *fn_k18 *fn_k24 *fn_k23 *fn_k11 *fn_k12 *fn_k9 *fn_k10 * *(num) * /(num) * +(num) * -(num) *num lock *7 home *9 pgup *8 *fn_k5 *fn_k1 *fn_k13 fn *fn_k14 notice: ?return key? must be forced to port2 for remote wake up function. if not, remote wake up function will not work. * : for fn key model usage
nt68p81 25 fn key model usage for keypad fn+scroll lock num lock fn+& 7 7 home fn+* 8 8 - fn + ( 9 9 pgup fn+) 0 *(num) fn+u 4 ? fn+i 5(num) fn+o 6 ? fn+p - (num) fn+j 1 end fn+k 2 fn+l 3 pgdn fn+: ; +(num) fn+m 0 ins fn+> . . del fn+? / /(num) fn key model usage for consumer keys fn_k1 fn+f1 www backward fn_k2 fn+f2 www forward fn_k3 fn+f3 www stop fn_k4 fn+f4 www refresh fn_k5 fn+f5 www search fn_k6 fn+f6 www favorite fn_k7 fn+f7 www home f n_k8 fn+f8 email fn_k9 fn+f9 my computer fn_k10 fn+f10 calculator fn_k11 fn+f11 media select fn_k12 fn+f12 mute fn_k13 fn+print screen bass boost fn_k14 fn+pause sleep fn_k15 fn+insert volume+ fn_k16 fn+home bass+ fn_k17 fn+page up treble+ fn_k18 fn+d elete volume - fn_k19 fn+end bass - fn_k20 fn+page down treble - fn_k21 fn+ - stop fn_k22 fn+ ? scan previous track fn_k23 fn+ play/pause fn_k24 fn+ ? scan next track
nt68p81 26 bonding diagram substrate connect to vcc unit: m m pad no. designation x y 1 gnd 264.50 - 2460.05 2 gnd 424.50 - 2481.00 3 vcp 734.95 - 2470.00 4 vdp 1069.35 - 2466.00 5 vdm 1368.85 - 2466.00 6 p30 1443.05 - 2069.05 7 p31 1443.05 - 1768.65 8 p32 1443.05 - 1468.25 9 p33 1443.05 - 1167.85 10 p34 14 43.05 - 867.45 11 reset 1443.05 - 560.45 12 p00 1443.05 - 235.35 13 p01 1443.05 65.05 14 p02 1443.05 365.45 15 p03 1443.05 659.85 16 p04 1443.05 1007.20 17 p05 1463.90 2545.00 18 p06 1173.90 2545.00 19 p07 883.90 2545.00 20 p10 593.90 2 545.00 21 p11 303.90 2545.00 pad no. designation x y 22 p12 - 308.10 2545.00 23 p13 - 598.10 2545.00 24 p14 - 888.10 2545.00 25 p15 - 1178.10 2545.00 26 p16 - 1478.00 1012.50 27 p17 - 1478.00 670.80 28 p20 - 1478.00 370.40 29 p21 - 1478.00 70.00 30 p22 - 1478.00 - 230.40 31 p23 - 1478.00 - 530.80 32 p24 - 1478.00 - 831.20 33 p25 - 1478.00 - 1131.60 34 p26 - 1478.00 - 1432.00 35 p27 - 1478.00 - 1732.40 36 led0 - 1478.00 - 2037.15 37 led1 - 1478.00 - 2337.55 38 led2 - 1112.85 - 2481.00 39 vcc - 812.45 - 2470.55 40 vcc - 626.85 - 2470.55 led1 led0 18 19 20 21 22 23 24 25 17 p05 p06 p07 p10 p12 p13 p14 p15 p11 16 15 14 13 12 11 10 9 8 7 6 p04 p03 p02 p01 p00 reset b p34 p33 p32 p31 p30 5 4 3 2 1 42 41 40 39 38 vdm vdp vcp gnd gnd osci osco vcc vcc led2 26 27 28 29 30 31 32 33 34 35 36 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 37 nt68p81 (0,0) 5470 m m 3400 m m
nt68p81 27 41 osco - 326.45 - 2481.00 42 osci - 7.75 - 2481.00
nt68p81 28 ordering information part no. packages nt68p81h chip form nt68p81 40l dip standard code functional descriptions code number name reference application circuit functional descri ption nt68 p 81 - d01012 simple keyboard with ps/2 mouse application circuit 1 1. ps/2 mouse port 2. '000' and '00' keys nt68 p 81 - d01013 windows 2000 compatible keyboard application circuit 2 1. acpi keys 2. '000', '00' and euro keys 3. consumer keys (windows 2000 ) nt68 p 81 - d01014 mini keyboard application circuit 3 1. acpi keys 2. ? 000 ? , ? 00 ? and euro keys 3. consumer keys (windows 2000) 4. fn key and 4 0 translated keys
nt68p81 29 package information p - dip 40l outline dimensions unit: inches/mm 1 21 40 e 1 s a 2 a l e e a d c a b 1 b a 1 base plane seating plane 20 e 1 s ymbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.1550.010 3.940.25 b 0.018 +0.004 0.46 +0.10 - 0.002 - 0.05 b 1 0.050 +0.004 1.27 +0.10 - 0.002 - 0.05 c 0.010 +0.004 0.25 +0.10 - 0.002 - 0.05 d 2 .055 typ. (2.075 max.) 52.20 typ. (52.71 max.) e 0.6000.010 15.240.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.1000.010 2.540.25 l 0.1300.010 3.300.25 \ 0~ 15 0~ 15 e a 0.6550.035 16.640.89 s 0.093 max. 2.36 max. note: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash.
nt68p81 30 product spec. change notice nt68p81 spec ification revision history version content data 2.1 fn key model usage for consumer keys modified - fn_k22 and fn_k24 (page 24) oct. 2002 2.0 volume knob application deleted (page 18) ps/2 mouse application added (page 18 and 19) application circuit 2 a nd 3 modified (page 22 and 23) fn key usage added (page 24 ) standard code functional descriptions modified (page 26) sep. 2002 1.3 application circuits modified (page 20, 21 and 22) standard code functional description added (page 24) july 2002 1.0 origi nal nov. 1998

▲Up To Search▲

Price & Availability of NT68P81-D01012

	To Download NT68P81-D01012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .